San. Disk Ultra II (2. GB) SSD Review. Two years ago Samsung dropped the bomb by releasing the first TLC NAND based SSD. I still vividly remember Anand's reaction when I told him about the SSD 8. I was in Korea for the launch event and was sitting in a press room where Samsung held the announcement.
Samsung had only sampled us and everyone else with the 8. Pro, so the 8. 40 and its guts had remained as a mystery.
As soon as Samsung lifted the curtain on the 8. I shot Anand a message telling him that it was TLC NAND based. The reason why I still remember this so clearly is because I had to tell Anand three times that, . Most of the other manufacturers have talked about TLC SSDs in one way or another, but nobody has come up with anything retail worthy.. A month ago San. Disk took the stage and unveiled their Ultra II, the company's first TLC SSD and the first TLC SSD that is not by Samsung. Obviously, there's a lot to discuss, but let's start with a quick overview of TLC and the market landscape.
There are a variety of reasons for Samsung's head start in the TLC game. Samsung is the only client SSD manufacturer with a fully integrated business model: everything inside Samsung SSDs is designed and manufactured by Samsung. That is unique in the industry because even though the likes of San. Disk and Micron/Crucial manufacture NAND and develop their own custom firmware, they rely on Marvell's controllers for their client drives. Third party silicon always creates some limitations because it is designed based on the needs of several customers, whereas in- house silicon can be designed for a specific application and firmware architecture. Furthermore, Samsung is the only NAND manufacturer in addition to SK Hynix that is not in a NAND joint- venture.
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Without a partner Samsung has the full freedom to dedicate as much (or as little) resources and fab space to TLC development and production as necessary, while San. Disk must coordinate with Toshiba to ensure that both companies are satisfied with the development and production strategy. From what I have heard, the two major problems with TLC have been late production ramp up and low volume. In other words, it has taken two or three additional quarters for TLC NAND to become mature enough for SSDs compared to MLC NAND at the same node, which means that a new MLC node is already sampling and will be available for SSD use within a couple of quarters. It has simply made sense to wait for the smaller and more cost efficent MLC node to become available instead of focusing development resources on a TLC SSD that would become obsolete in a matter of months. San. Disk and Toshiba seem to have revised their strategy, though, because their second generation 1. TLC is already SSD- grade and the production of both MLC and TLC flavors of the 1.
Two years ago Samsung dropped the bomb by releasing the first TLC NAND based SSD. I still vividly remember Anand's reaction when I told him about the SSD 840. Gratis-Software Die 5 besten kostenlosen SSD-Tools für Ihre High-Speed-Laufwerke.
Maybe TLC is finally becoming a first class citizen in the fab world. Today's review will help tell us more about the state of TLC NAND outside of Samsung's world. I am not going to cover the technical aspects of TLC here because we have done that severaltimes before, so take a look at the links in case you need a refresh on how TLC works and how it differs from SLC/MLC. The Ultra II is available in four capacities: 1. GB, 2. 40. GB, 4. GB and 9. 60. GB.
The 1. 20. GB and 2. GB models are shipping already, but the larger 4. GB and 9. 60. GB models will be available in about a month. All come in a 2. 5. There are no m. SATA or M. I was told there are not any in the pipeline either (at least for retail). San. Disk has always been rather conservative with their retail lineup and they have not been interested in the small niches that m.
SATA and M. 2 currently offer, so it is logical decision to stick with 2. To my knowledge there is not any difference besides the channel count (perhaps in internal cache sizes too), and the . San. Disk has done this before with the X3. Note that the 9. 18. TLC- optimized 1.
Marvell – it is the same controller that is used in Crucial's MX1. Similar to the rest of San. Disk's client SSD lineup, the Ultra II does not offer any encryption support. For now San. Disk is only offering encryption in the X3. TCG Opal 2. 0 and e. Drive support will very likely make their way to the client drives as well.
Dev. Sleep is not supported either and San. Disk said the reason is that the niche for aftermarket Dev. Sleep- enabled SSDs is practically non- existent. Nearly all platforms that support Dev. Sleep (which is very few, actually) already come with SSDs, e.
The secret behind the performance is the new n. Cache 2. 0, which takes San. Disk's pseudo- SLC caching mode to a next level. While the original n. Cache was mainly designed for caching the NAND mapping table along with some small writes (< 4. KB), the 2. 0 version caches all writes regardless of their size and type by increasing the capacity of the pseudo- SLC portion.
The benefit is that when data has to be moved from the SLC to the TLC portion, the transfer can be done internally in the die, which is a feature San. Disk calls On Chip Copy. This is a proprietary design and uses a special die, so you will not see any competitive products using the same architecture.
Normally the SLC to TLC transfer would be done like any other wear- leveling operation by using the NAND interface (Toggle or ONFI) and DRAM to move the data around internally from die to die, but the downside is that such a design may interrupt host IO processing since the internal operations occupy the NAND interface and DRAM. OCZ's . Performance recovers once the copy/reorganize operations are complete. San. Disk's approach introduces minimal overhead because everything is done within the die. Since an SLC block is exactly one third of a TLC block, three SLC blocks are simply folded into one TLC block. Obviously there is still some additional latency if you are trying to access a page in a block that is in the middle of the folding operation, but the impact of that is far smaller than what a die- to- die transfer would cause. The On Chip Copy has a predefined threshold that will trigger the folding mechanism, although San.
Disk said that it is adaptive in the sense that it will also look at the data type and size to determine the best action. Idle time will also trigger On Chip Copy, but there is no set threshold for that either from what I was told. In our 2. 40. GB sample the SLC cache size is 1. GB and since sixteen 1. Gbit (1. 6Gi. B) NAND dies are needed for the raw NAND capacity of 2.
Gi. B, the cache per die works out to be 6. MB. I am guessing that in reality there is 3. Gi. B of TLC NAND running in SLC mode (i. Gi. B per die), which would mean 1.
Gi. B of SLC, but unfortunately San. Disk could not share the exact block sizes of TLC and MLC with us for competitive reasons. The performance benefits of the SLC mode are obvious. A TLC block requires multiple iterations to be programmed because the distribution of the voltage states is much narrower, so there is less room for errors, which needs a longer and more complex programming process. I ran HD Tach to see what the performance is across all LBAs. With sequential data the threshold for On Chip Copy seems to be about 8. GB because after that the performance drops from 4.
MB to ~2. 30. MB/s. For average client workloads that is more than enough because users do not usually write more than ~1. GB per day and with idle time n. Cache 2. 0 will also move data from SLC to TLC to ensure that the SLC cache has enough space for all incoming writes. The improved performance is not the only benefit of n. Cache 2. 0. Because everything gets written to the SLC portion first, the data can then be written sequentially to TLC.
That minimizes write amplification on the TLC part, which in turn increases endurance because there will be less redundant NAND writes. With sequential writes it is typically possible to achieve write amplification of very close to 1x (i. That is because not all data makes it to the TLC in the first place – some data will be deleted while it is still in the SLC cache and thus will not cause any wear on the TLC. Remember, TLC is generally only good for about 5. P/E cycles, whereas SLC can easily surpass 3.
SLC cache as much as possible is crucial for endurance with TLC at such small lithographies. Like the previous n.
Cache 1. 0, the 2. NAND mapping table to prevent data corruption and loss. San. Disk does not employ any power loss protection circuitry (i.
That obviously does not provide the same level of protection as capacitors do because all writes in progress will be lost during a power failure, but it ensures that the NAND mapping table will not become corrupt and turn the drive into a brick. San. Disk actually has an extensive whitepaper on power loss protection and the techniques that are used, so those who are interested in the topic should find it a good read. Multi Page Recovery (M. P. R)Using parity as a form of error correction has become more and more popular in the industry lately. Sand. Force made the first move with RAISE several years ago and nearly every manufacturer has released their own implementation since then. However, San. Disk has been one of the few that have not had any proper parity- based error correction in client SSDs, but the Ultra II changes that. San. Disk's implementation is called Multi Page Recovery and as the name suggests, it provides page- level redundancy.
The idea is exactly the same as with Sand. Force's RAISE, Micron's RAIN, and any other RAID 5- like scheme: parity is created for data that comes in, which can then be used to recover the data in case the ECC engine is not able to do it. The parity ratio in the Ultra II is 5: 1, which means that there is one parity page for every five pages of actual data. But here is the tricky part: with 2. Gi. B of raw NAND and a 5: 1 parity ratio, the usable capacity could not be more than 2. GB because one sixth of the NAND is dedicated for parity. The secret is that the NAND dies are not really 1.
Gbit – they are in fact much larger than that.